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237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 6171d 00h /ethmac/tags/rel_9/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6171d 00h /ethmac/tags/rel_9/
235 rev 4. mohor 6171d 15h /ethmac/tags/rel_9/
234 Figure list assed to the revision 3. mohor 6171d 23h /ethmac/tags/rel_9/
233 Revision 0.3 released. Some figures added. mohor 6171d 23h /ethmac/tags/rel_9/
232 fpga define added. mohor 6176d 18h /ethmac/tags/rel_9/
231 Description of Core Modules added (figure). mohor 6178d 20h /ethmac/tags/rel_9/
229 case changed to casex. mohor 6182d 16h /ethmac/tags/rel_9/
227 Changed BIST scan signals. tadejm 6182d 20h /ethmac/tags/rel_9/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6182d 21h /ethmac/tags/rel_9/
225 Some minor changes. tadejm 6182d 22h /ethmac/tags/rel_9/
224 Signals for a wave window in Modelsim. tadejm 6182d 23h /ethmac/tags/rel_9/
223 Some code changed due to bug fixes. tadejm 6182d 23h /ethmac/tags/rel_9/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6186d 21h /ethmac/tags/rel_9/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6189d 22h /ethmac/tags/rel_9/
218 Typo error fixed. (When using Bist) mohor 6190d 00h /ethmac/tags/rel_9/
217 Bist supported. mohor 6190d 00h /ethmac/tags/rel_9/
216 Bist signals added. mohor 6190d 00h /ethmac/tags/rel_9/
215 Bist supported. mohor 6190d 00h /ethmac/tags/rel_9/
214 Signals for WISHBONE B3 compliant interface added. mohor 6190d 20h /ethmac/tags/rel_9/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6190d 20h /ethmac/tags/rel_9/
212 Minor $display change. mohor 6190d 20h /ethmac/tags/rel_9/
211 Bist added. mohor 6190d 21h /ethmac/tags/rel_9/
210 BIST added. mohor 6190d 21h /ethmac/tags/rel_9/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6192d 00h /ethmac/tags/rel_9/
208 Virtual Silicon RAMs moved to lib directory tadej 6207d 18h /ethmac/tags/rel_9/
207 Virtual Silicon RAM support fixed tadej 6207d 18h /ethmac/tags/rel_9/
206 Virtual Silicon RAM added to the simulation. mohor 6207d 18h /ethmac/tags/rel_9/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 6207d 19h /ethmac/tags/rel_9/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6207d 19h /ethmac/tags/rel_9/

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