Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_9/] [rtl/] - Rev 134


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 7525d 02h /ethmac/tags/rel_9/rtl/
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 7525d 03h /ethmac/tags/rel_9/rtl/
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7525d 03h /ethmac/tags/rel_9/rtl/
131 LinkFail signal was not latching appropriate bit. mohor 7525d 03h /ethmac/tags/rel_9/rtl/
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 7525d 04h /ethmac/tags/rel_9/rtl/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7545d 03h /ethmac/tags/rel_9/rtl/
126 InvalidSymbol generation changed. mohor 7545d 03h /ethmac/tags/rel_9/rtl/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
mohor 7545d 03h /ethmac/tags/rel_9/rtl/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7547d 05h /ethmac/tags/rel_9/rtl/
120 Unused files removed. mohor 7547d 06h /ethmac/tags/rel_9/rtl/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7547d 06h /ethmac/tags/rel_9/rtl/
118 ShiftEnded synchronization changed. mohor 7550d 20h /ethmac/tags/rel_9/rtl/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7552d 05h /ethmac/tags/rel_9/rtl/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7553d 02h /ethmac/tags/rel_9/rtl/
113 RxPointer bug fixed. mohor 7559d 18h /ethmac/tags/rel_9/rtl/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7560d 08h /ethmac/tags/rel_9/rtl/
111 Master state machine had a bug when switching from master write to
master read.
mohor 7560d 21h /ethmac/tags/rel_9/rtl/
110 m_wb_cyc_o signal released after every single transfer. mohor 7561d 00h /ethmac/tags/rel_9/rtl/
109 Comment removed. mohor 7561d 01h /ethmac/tags/rel_9/rtl/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7628d 11h /ethmac/tags/rel_9/rtl/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7637d 12h /ethmac/tags/rel_9/rtl/
104 FCS should not be included in NibbleMinFl. mohor 7639d 06h /ethmac/tags/rel_9/rtl/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 7639d 07h /ethmac/tags/rel_9/rtl/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 7639d 07h /ethmac/tags/rel_9/rtl/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 7639d 07h /ethmac/tags/rel_9/rtl/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 7639d 07h /ethmac/tags/rel_9/rtl/
97 Small typo fixed. lampret 7663d 05h /ethmac/tags/rel_9/rtl/
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 7667d 05h /ethmac/tags/rel_9/rtl/
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 7667d 08h /ethmac/tags/rel_9/rtl/
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 7667d 08h /ethmac/tags/rel_9/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2023, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.