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[/] [ethmac/] [tags/] [rel_9/] [rtl/] [verilog/] [eth_macstatus.v] - Rev 338

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Rev Log message Author Age Path
338 root 5468d 11h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v
335 New directory structure. root 5525d 16h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7847d 13h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7895d 11h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v
146 CarrierSenseLost status is not set when working in loopback mode. mohor 7903d 07h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v
126 InvalidSymbol generation changed. mohor 7944d 08h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8038d 12h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v
70 Small fixes. mohor 8101d 15h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8104d 09h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v
43 Tx status is written back to the BD. mohor 8108d 17h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v
42 Rx status is written back to the BD. mohor 8111d 10h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v
37 Link in the header changed. mohor 8127d 16h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8223d 17h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v
18 Few little NCSIM warnings fixed. mohor 8261d 12h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8297d 11h /ethmac/tags/rel_9/rtl/verilog/eth_macstatus.v

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