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[/] [ethmac/] [tags/] [runing_under_uclinux/] - Rev 338

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338 root 3866d 12h /ethmac/tags/runing_under_uclinux
335 New directory structure. root 3923d 17h /ethmac/tags/runing_under_uclinux
144 This commit was manufactured by cvs2svn to create tag
'runing_under_uclinux'.
6317d 11h /ethmac/tags/runing_under_uclinux
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
mohor 6317d 11h /ethmac/tags/runing_under_uclinux
141 Syntax error fixed. mohor 6320d 05h /ethmac/tags/runing_under_uclinux
140 Syntax error fixed. mohor 6320d 05h /ethmac/tags/runing_under_uclinux
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 6320d 05h /ethmac/tags/runing_under_uclinux
138 Synchronous reset added. mohor 6320d 05h /ethmac/tags/runing_under_uclinux
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.
mohor 6320d 05h /ethmac/tags/runing_under_uclinux
136 Parameter ResetValue changed to capital letters. mohor 6320d 15h /ethmac/tags/runing_under_uclinux
135 New revision. External DMA removed, TX_BD_NUM changed. mohor 6322d 06h /ethmac/tags/runing_under_uclinux
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 6322d 08h /ethmac/tags/runing_under_uclinux
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 6322d 09h /ethmac/tags/runing_under_uclinux
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 6322d 09h /ethmac/tags/runing_under_uclinux
131 LinkFail signal was not latching appropriate bit. mohor 6322d 09h /ethmac/tags/runing_under_uclinux
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.
mohor 6322d 09h /ethmac/tags/runing_under_uclinux
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 6322d 10h /ethmac/tags/runing_under_uclinux
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 6342d 09h /ethmac/tags/runing_under_uclinux
126 InvalidSymbol generation changed. mohor 6342d 09h /ethmac/tags/runing_under_uclinux
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 6342d 09h /ethmac/tags/runing_under_uclinux

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