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[/] [ethmac/] [trunk/] - Rev 368


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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 4004d 20h /ethmac/trunk
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 4067d 17h /ethmac/trunk
366 Readded eth_top.v with a deprecation warning olof 4191d 21h /ethmac/trunk
365 Whitespace cleanup olof 4192d 20h /ethmac/trunk
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4193d 18h /ethmac/trunk
360 Added partial implementation of the debug register from ORPSoC olof 4195d 01h /ethmac/trunk
359 Verilator linting fixes olof 4197d 04h /ethmac/trunk
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4198d 18h /ethmac/trunk
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4198d 18h /ethmac/trunk
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4198d 20h /ethmac/trunk
355 Import Julius Baxter's verilator hints from ORPSoC olof 4198d 20h /ethmac/trunk
354 Whitespace cleanup olof 4198d 21h /ethmac/trunk
353 Inherit fixes for bit width of constants from ORPSoC olof 4200d 22h /ethmac/trunk
352 Removed delayed assignments from rtl code olof 4205d 04h /ethmac/trunk
351 Turn defines into parameters in eth_cop olof 4213d 18h /ethmac/trunk
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4213d 19h /ethmac/trunk
349 Make all parameters configurable from top level olof 4214d 19h /ethmac/trunk
348 Added option to dump VCD files olof 4215d 18h /ethmac/trunk
347 Added information about running with Icarus Verilog olof 4215d 19h /ethmac/trunk
346 Updated project location olof 4215d 21h /ethmac/trunk

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