OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] - Rev 185

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
185 Directory keeper. mohor 7862d 16h /ethmac/trunk/
184 Modelsim simulation environment should be ready now. mohor 7862d 16h /ethmac/trunk/
183 Modelsim environment added. mohor 7862d 16h /ethmac/trunk/
182 Full duplex test improved. tadej 7863d 17h /ethmac/trunk/
181 MIIM test look better. mohor 7863d 20h /ethmac/trunk/
180 Bench outputs data to display every 128 bytes. mohor 7866d 15h /ethmac/trunk/
179 Beautiful tests merget together mohor 7866d 16h /ethmac/trunk/
178 Rearanged testcases mohor 7866d 16h /ethmac/trunk/
177 Bug in MIIM fixed. mohor 7866d 20h /ethmac/trunk/
176 lists changed to new directory structure mohor 7866d 22h /ethmac/trunk/
175 Script fixed to new dir structure mohor 7866d 22h /ethmac/trunk/
174 Directory keeper mohor 7866d 22h /ethmac/trunk/
173 Keeps the directory mohor 7866d 22h /ethmac/trunk/
172 NCSIM simulation environment added to cvs mohor 7866d 22h /ethmac/trunk/
171 NCSIM simulation environment added. mohor 7866d 22h /ethmac/trunk/
170 Headers changed. mohor 7866d 22h /ethmac/trunk/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7866d 23h /ethmac/trunk/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7867d 20h /ethmac/trunk/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7868d 20h /ethmac/trunk/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 7869d 21h /ethmac/trunk/
165 HASH improvement needed. mohor 7870d 00h /ethmac/trunk/
164 Ethernet debug registers removed. mohor 7870d 00h /ethmac/trunk/
163 Another temporary version. Core is almost finished. Testbench not included,
yet"
mohor 7870d 16h /ethmac/trunk/
162 Another temporary version. Core is almost finished. Testbench not included,
yet.
mohor 7870d 16h /ethmac/trunk/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7870d 22h /ethmac/trunk/
160 error acknowledge cycle termination added to display. mohor 7870d 22h /ethmac/trunk/
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 7871d 18h /ethmac/trunk/
158 Typo fixed. mohor 7871d 18h /ethmac/trunk/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7874d 00h /ethmac/trunk/
156 Valid testbench. mohor 7874d 00h /ethmac/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.