OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] - Rev 235

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
235 rev 4. mohor 7848d 10h /ethmac/trunk/
234 Figure list assed to the revision 3. mohor 7848d 18h /ethmac/trunk/
233 Revision 0.3 released. Some figures added. mohor 7848d 18h /ethmac/trunk/
232 fpga define added. mohor 7853d 13h /ethmac/trunk/
231 Description of Core Modules added (figure). mohor 7855d 14h /ethmac/trunk/
229 case changed to casex. mohor 7859d 11h /ethmac/trunk/
227 Changed BIST scan signals. tadejm 7859d 15h /ethmac/trunk/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7859d 16h /ethmac/trunk/
225 Some minor changes. tadejm 7859d 16h /ethmac/trunk/
224 Signals for a wave window in Modelsim. tadejm 7859d 18h /ethmac/trunk/
223 Some code changed due to bug fixes. tadejm 7859d 18h /ethmac/trunk/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7863d 16h /ethmac/trunk/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7866d 16h /ethmac/trunk/
218 Typo error fixed. (When using Bist) mohor 7866d 18h /ethmac/trunk/
217 Bist supported. mohor 7866d 18h /ethmac/trunk/
216 Bist signals added. mohor 7866d 18h /ethmac/trunk/
215 Bist supported. mohor 7866d 19h /ethmac/trunk/
214 Signals for WISHBONE B3 compliant interface added. mohor 7867d 15h /ethmac/trunk/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7867d 15h /ethmac/trunk/
212 Minor $display change. mohor 7867d 15h /ethmac/trunk/
211 Bist added. mohor 7867d 15h /ethmac/trunk/
210 BIST added. mohor 7867d 15h /ethmac/trunk/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7868d 19h /ethmac/trunk/
208 Virtual Silicon RAMs moved to lib directory tadej 7884d 12h /ethmac/trunk/
207 Virtual Silicon RAM support fixed tadej 7884d 13h /ethmac/trunk/
206 Virtual Silicon RAM added to the simulation. mohor 7884d 13h /ethmac/trunk/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7884d 13h /ethmac/trunk/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7884d 13h /ethmac/trunk/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7884d 14h /ethmac/trunk/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7887d 15h /ethmac/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.