OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] - Rev 268

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
268 Release 1.19. Control frame description changed. mohor 7792d 09h /ethmac/trunk
267 Full duplex control frames tested. mohor 7792d 12h /ethmac/trunk
266 Flow control test almost finished. mohor 7797d 11h /ethmac/trunk
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 7797d 15h /ethmac/trunk
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 7798d 02h /ethmac/trunk
262 Version 1.18 released.
MIIMRST (Reset of the MIIM module) not used any more in the MIIMODER
register. Control Frame bit (CF) added to the RX buffer descriptor. Control
frame detection section updated.
mohor 7798d 02h /ethmac/trunk
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7798d 02h /ethmac/trunk
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7798d 14h /ethmac/trunk
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 7799d 04h /ethmac/trunk
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 7799d 04h /ethmac/trunk
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 7799d 04h /ethmac/trunk
255 TPauseRq synchronized to tx_clk. mohor 7799d 04h /ethmac/trunk
254 Temp version. mohor 7800d 08h /ethmac/trunk
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7800d 10h /ethmac/trunk
252 Just some updates. tadejm 7800d 10h /ethmac/trunk
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 7800d 10h /ethmac/trunk
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7800d 10h /ethmac/trunk
248 wb_rst_i is used for MIIM reset. mohor 7801d 11h /ethmac/trunk
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7804d 14h /ethmac/trunk
245 Rev 1.7. mohor 7805d 07h /ethmac/trunk

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.