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Rev Log message Author Age Path
338 root 4432d 10h /ethmac/trunk/
335 New directory structure. root 4489d 16h /ethernet/trunk/
334 Minor fixes for Icarus simulator. igorm 5937d 18h /trunk/
333 Some small fixes + some troubles fixed. igorm 5938d 05h /trunk/
332 Case statement improved for synthesys. igorm 5951d 11h /trunk/
331 Tests for delayed CRC and defer indication added. igorm 5966d 13h /trunk/
330 Warning fixes. igorm 5966d 13h /trunk/
329 Defer indication fixed. igorm 5966d 14h /trunk/
328 Delayed CRC fixed. igorm 5966d 14h /trunk/
327 Defer indication fixed. igorm 5966d 14h /trunk/
326 Delayed CRC fixed. igorm 5966d 15h /trunk/
325 Defer indication fixed. igorm 5966d 15h /trunk/
323 Accidently deleted line put back. igorm 6263d 15h /trunk/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 6267d 10h /trunk/
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 6267d 14h /trunk/
319 Latest Ethernet IP core testbench. tadejm 6298d 09h /trunk/
318 Latest Ethernet IP core testbench. tadejm 6298d 10h /trunk/
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 6307d 16h /trunk/
315 Updated testbench. Some more testcases, some repaired. tadejm 6410d 13h /trunk/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 6410d 13h /trunk/
311 Update script for running different file list files for different RAM models. tadejm 6410d 13h /trunk/
310 More signals. tadejm 6410d 13h /trunk/
309 Update file list files for different RAM models with byte select accessing. tadejm 6410d 13h /trunk/
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 6410d 13h /trunk/
306 Lapsus fixed (!we -> ~we). simons 6411d 11h /trunk/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 6433d 07h /trunk/
302 mbist signals updated according to newest convention markom 6459d 18h /trunk/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 6470d 10h /trunk/
299 Artisan RAMs added. mohor 6517d 13h /trunk/
297 Artisan ram instance added. simons 6523d 09h /trunk/

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