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Rev Log message Author Age Path
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 7662d 04h /ethmac/trunk/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 7662d 08h /ethmac/trunk/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 7662d 08h /ethmac/trunk/
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 7662d 09h /ethmac/trunk/
30 BD section updated. mohor 7664d 06h /ethmac/trunk/
29 Generic memory model is used. Defines are changed for the same reason. mohor 7684d 04h /ethmac/trunk/
28 New release. Name changed to lower case. mohor 7686d 20h /ethmac/trunk/
27 File names changed to lower case. mohor 7686d 20h /ethmac/trunk/
26 First release of product brief. mohor 7686d 20h /ethmac/trunk/
25 First release of product brief. mohor 7686d 20h /ethmac/trunk/
24 Log file added. mohor 7709d 07h /ethmac/trunk/
23 Number of addresses (wb_adr_i) minimized. mohor 7709d 07h /ethmac/trunk/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7709d 10h /ethmac/trunk/
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 7710d 07h /ethmac/trunk/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 7734d 04h /ethmac/trunk/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 7734d 04h /ethmac/trunk/
18 Few little NCSIM warnings fixed. mohor 7747d 05h /ethmac/trunk/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 7774d 05h /ethmac/trunk/
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 7781d 10h /ethmac/trunk/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7783d 04h /ethmac/trunk/

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