Subversion Repositories ethmac

[/] [ethmac/] [trunk/] - Rev 344


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
344 bit 9 in phy control register is self clearing olof 4456d 19h /ethmac/trunk/
343 Address miss should not be asserted on short frames olof 4460d 15h /ethmac/trunk/
342 Added cast to avoid inequality when comparing different data types olof 4460d 16h /ethmac/trunk/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4460d 16h /ethmac/trunk/
340 Don't fail if log dir already exists olof 4461d 13h /ethmac/trunk/
339 Added basic support for Icarus Verilog olof 4462d 13h /ethmac/trunk/
338 root 5254d 18h /ethmac/trunk/
335 New directory structure. root 5311d 23h /ethernet/trunk/
334 Minor fixes for Icarus simulator. igorm 6760d 02h /trunk/
333 Some small fixes + some troubles fixed. igorm 6760d 13h /trunk/
332 Case statement improved for synthesys. igorm 6773d 19h /trunk/
331 Tests for delayed CRC and defer indication added. igorm 6788d 20h /trunk/
330 Warning fixes. igorm 6788d 21h /trunk/
329 Defer indication fixed. igorm 6788d 22h /trunk/
328 Delayed CRC fixed. igorm 6788d 22h /trunk/
327 Defer indication fixed. igorm 6788d 22h /trunk/
326 Delayed CRC fixed. igorm 6788d 22h /trunk/
325 Defer indication fixed. igorm 6788d 23h /trunk/
323 Accidently deleted line put back. igorm 7085d 23h /trunk/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 7089d 18h /trunk/
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 7089d 22h /trunk/
319 Latest Ethernet IP core testbench. tadejm 7120d 17h /trunk/
318 Latest Ethernet IP core testbench. tadejm 7120d 18h /trunk/
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7130d 00h /trunk/
315 Updated testbench. Some more testcases, some repaired. tadejm 7232d 21h /trunk/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7232d 21h /trunk/
311 Update script for running different file list files for different RAM models. tadejm 7232d 21h /trunk/
310 More signals. tadejm 7232d 21h /trunk/
309 Update file list files for different RAM models with byte select accessing. tadejm 7232d 21h /trunk/
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 7232d 21h /trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2023, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.