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Rev Log message Author Age Path
360 Added partial implementation of the debug register from ORPSoC olof 4728d 01h /ethmac/trunk/
359 Verilator linting fixes olof 4730d 03h /ethmac/trunk/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4731d 17h /ethmac/trunk/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4731d 18h /ethmac/trunk/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4731d 19h /ethmac/trunk/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4731d 20h /ethmac/trunk/
354 Whitespace cleanup olof 4731d 21h /ethmac/trunk/
353 Inherit fixes for bit width of constants from ORPSoC olof 4733d 22h /ethmac/trunk/
352 Removed delayed assignments from rtl code olof 4738d 04h /ethmac/trunk/
351 Turn defines into parameters in eth_cop olof 4746d 18h /ethmac/trunk/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4746d 18h /ethmac/trunk/
349 Make all parameters configurable from top level olof 4747d 19h /ethmac/trunk/
348 Added option to dump VCD files olof 4748d 18h /ethmac/trunk/
347 Added information about running with Icarus Verilog olof 4748d 19h /ethmac/trunk/
346 Updated project location olof 4748d 21h /ethmac/trunk/
345 Temporarily disable failing tests olof 4748d 22h /ethmac/trunk/
344 bit 9 in phy control register is self clearing olof 4755d 00h /ethmac/trunk/
343 Address miss should not be asserted on short frames olof 4758d 20h /ethmac/trunk/
342 Added cast to avoid inequality when comparing different data types olof 4758d 20h /ethmac/trunk/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4758d 21h /ethmac/trunk/

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