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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 188

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Rev Log message Author Age Path
188 PHY changed. tadej 7881d 21h /ethmac/trunk/bench/verilog/
182 Full duplex test improved. tadej 7882d 23h /ethmac/trunk/bench/verilog/
181 MIIM test look better. mohor 7883d 02h /ethmac/trunk/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 7885d 22h /ethmac/trunk/bench/verilog/
179 Beautiful tests merget together mohor 7885d 23h /ethmac/trunk/bench/verilog/
178 Rearanged testcases mohor 7885d 23h /ethmac/trunk/bench/verilog/
177 Bug in MIIM fixed. mohor 7886d 03h /ethmac/trunk/bench/verilog/
170 Headers changed. mohor 7886d 05h /ethmac/trunk/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7886d 05h /ethmac/trunk/bench/verilog/
158 Typo fixed. mohor 7891d 01h /ethmac/trunk/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7893d 06h /ethmac/trunk/bench/verilog/
156 Valid testbench. mohor 7893d 06h /ethmac/trunk/bench/verilog/
155 Minor changes. mohor 7893d 06h /ethmac/trunk/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7936d 00h /ethmac/trunk/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7938d 01h /ethmac/trunk/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 7942d 03h /ethmac/trunk/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7942d 03h /ethmac/trunk/bench/verilog/
108 Testbench supports unaligned accesses. mohor 8019d 07h /ethmac/trunk/bench/verilog/
107 TX_BUF_BASE changed. mohor 8019d 07h /ethmac/trunk/bench/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8064d 04h /ethmac/trunk/bench/verilog/

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