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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 302

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Rev Log message Author Age Path
302 mbist signals updated according to newest convention markom 7691d 22h /ethmac/trunk/bench/verilog/
299 Artisan RAMs added. mohor 7749d 18h /ethmac/trunk/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 7817d 18h /ethmac/trunk/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7950d 14h /ethmac/trunk/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7951d 17h /ethmac/trunk/bench/verilog/
274 Backup version. Not fully working. tadejm 7959d 11h /ethmac/trunk/bench/verilog/
267 Full duplex control frames tested. mohor 8015d 14h /ethmac/trunk/bench/verilog/
266 Flow control test almost finished. mohor 8020d 13h /ethmac/trunk/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 8021d 04h /ethmac/trunk/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 8021d 16h /ethmac/trunk/bench/verilog/
254 Temp version. mohor 8023d 10h /ethmac/trunk/bench/verilog/
252 Just some updates. tadejm 8023d 12h /ethmac/trunk/bench/verilog/
243 Late collision is not reported any more. tadejm 8028d 17h /ethmac/trunk/bench/verilog/
227 Changed BIST scan signals. tadejm 8055d 13h /ethmac/trunk/bench/verilog/
223 Some code changed due to bug fixes. tadejm 8055d 16h /ethmac/trunk/bench/verilog/
216 Bist signals added. mohor 8062d 17h /ethmac/trunk/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 8064d 17h /ethmac/trunk/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 8083d 16h /ethmac/trunk/bench/verilog/
192 Some additional reports added tadej 8085d 12h /ethmac/trunk/bench/verilog/
191 Bug repaired in eth_phy device tadej 8085d 12h /ethmac/trunk/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 8085d 14h /ethmac/trunk/bench/verilog/
188 PHY changed. tadej 8086d 10h /ethmac/trunk/bench/verilog/
182 Full duplex test improved. tadej 8087d 12h /ethmac/trunk/bench/verilog/
181 MIIM test look better. mohor 8087d 15h /ethmac/trunk/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 8090d 11h /ethmac/trunk/bench/verilog/
179 Beautiful tests merget together mohor 8090d 11h /ethmac/trunk/bench/verilog/
178 Rearanged testcases mohor 8090d 11h /ethmac/trunk/bench/verilog/
177 Bug in MIIM fixed. mohor 8090d 15h /ethmac/trunk/bench/verilog/
170 Headers changed. mohor 8090d 18h /ethmac/trunk/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 8090d 18h /ethmac/trunk/bench/verilog/

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