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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 357

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Rev Log message Author Age Path
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4647d 09h /ethmac/trunk/bench/verilog/
348 Added option to dump VCD files olof 4664d 08h /ethmac/trunk/bench/verilog/
346 Updated project location olof 4664d 11h /ethmac/trunk/bench/verilog/
345 Temporarily disable failing tests olof 4664d 12h /ethmac/trunk/bench/verilog/
344 bit 9 in phy control register is self clearing olof 4670d 14h /ethmac/trunk/bench/verilog/
343 Address miss should not be asserted on short frames olof 4674d 10h /ethmac/trunk/bench/verilog/
342 Added cast to avoid inequality when comparing different data types olof 4674d 10h /ethmac/trunk/bench/verilog/
338 root 5468d 13h /ethmac/trunk/bench/verilog/
335 New directory structure. root 5525d 18h /ethmac/trunk/bench/verilog/
334 Minor fixes for Icarus simulator. igorm 6973d 20h /ethmac/trunk/bench/verilog/
331 Tests for delayed CRC and defer indication added. igorm 7002d 15h /ethmac/trunk/bench/verilog/
318 Latest Ethernet IP core testbench. tadejm 7334d 12h /ethmac/trunk/bench/verilog/
315 Updated testbench. Some more testcases, some repaired. tadejm 7446d 15h /ethmac/trunk/bench/verilog/
302 mbist signals updated according to newest convention markom 7495d 20h /ethmac/trunk/bench/verilog/
299 Artisan RAMs added. mohor 7553d 16h /ethmac/trunk/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7621d 16h /ethmac/trunk/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7754d 12h /ethmac/trunk/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7755d 15h /ethmac/trunk/bench/verilog/
274 Backup version. Not fully working. tadejm 7763d 09h /ethmac/trunk/bench/verilog/
267 Full duplex control frames tested. mohor 7819d 12h /ethmac/trunk/bench/verilog/

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