URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 192

Rev	Log message	Author	Age	Path
192	Some additional reports added	tadej	7889d 12h	/ethmac/trunk/bench/verilog/tb_ethernet.v
182	Full duplex test improved.	tadej	7891d 12h	/ethmac/trunk/bench/verilog/tb_ethernet.v
181	MIIM test look better.	mohor	7891d 15h	/ethmac/trunk/bench/verilog/tb_ethernet.v
180	Bench outputs data to display every 128 bytes.	mohor	7894d 11h	/ethmac/trunk/bench/verilog/tb_ethernet.v
179	Beautiful tests merget together	mohor	7894d 11h	/ethmac/trunk/bench/verilog/tb_ethernet.v
178	Rearanged testcases	mohor	7894d 11h	/ethmac/trunk/bench/verilog/tb_ethernet.v
177	Bug in MIIM fixed.	mohor	7894d 15h	/ethmac/trunk/bench/verilog/tb_ethernet.v
170	Headers changed.	mohor	7894d 18h	/ethmac/trunk/bench/verilog/tb_ethernet.v
169	New testbench. Thanks to Tadej M - "The Spammer".	mohor	7894d 18h	/ethmac/trunk/bench/verilog/tb_ethernet.v
158	Typo fixed.	mohor	7899d 14h	/ethmac/trunk/bench/verilog/tb_ethernet.v
156	Valid testbench.	mohor	7901d 19h	/ethmac/trunk/bench/verilog/tb_ethernet.v
121	gsr added for use when ETH_XILINX_RAMB4 define is set.	mohor	7946d 14h	/ethmac/trunk/bench/verilog/tb_ethernet.v
117	Clock mrx_clk set to 2.5 MHz.	mohor	7950d 16h	/ethmac/trunk/bench/verilog/tb_ethernet.v
116	Testing environment also includes traffic cop, memory interface and host interface.	mohor	7950d 16h	/ethmac/trunk/bench/verilog/tb_ethernet.v