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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 263

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263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7818d 23h /ethmac/trunk/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7819d 11h /ethmac/trunk/bench/verilog/tb_ethernet.v
254 Temp version. mohor 7821d 05h /ethmac/trunk/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 7821d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 7826d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 7853d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 7853d 11h /ethmac/trunk/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7862d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 7881d 11h /ethmac/trunk/bench/verilog/tb_ethernet.v
192 Some additional reports added tadej 7883d 07h /ethmac/trunk/bench/verilog/tb_ethernet.v
182 Full duplex test improved. tadej 7885d 07h /ethmac/trunk/bench/verilog/tb_ethernet.v
181 MIIM test look better. mohor 7885d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
180 Bench outputs data to display every 128 bytes. mohor 7888d 06h /ethmac/trunk/bench/verilog/tb_ethernet.v
179 Beautiful tests merget together mohor 7888d 06h /ethmac/trunk/bench/verilog/tb_ethernet.v
178 Rearanged testcases mohor 7888d 07h /ethmac/trunk/bench/verilog/tb_ethernet.v
177 Bug in MIIM fixed. mohor 7888d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
170 Headers changed. mohor 7888d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7888d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
158 Typo fixed. mohor 7893d 09h /ethmac/trunk/bench/verilog/tb_ethernet.v
156 Valid testbench. mohor 7895d 14h /ethmac/trunk/bench/verilog/tb_ethernet.v

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