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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 345

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Rev Log message Author Age Path
345 Temporarily disable failing tests olof 5115d 21h /ethmac/trunk/bench/verilog/tb_ethernet.v
344 bit 9 in phy control register is self clearing olof 5121d 23h /ethmac/trunk/bench/verilog/tb_ethernet.v
343 Address miss should not be asserted on short frames olof 5125d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
342 Added cast to avoid inequality when comparing different data types olof 5125d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
338 root 5919d 22h /ethmac/trunk/bench/verilog/tb_ethernet.v
335 New directory structure. root 5977d 03h /ethmac/trunk/bench/verilog/tb_ethernet.v
334 Minor fixes for Icarus simulator. igorm 7425d 05h /ethmac/trunk/bench/verilog/tb_ethernet.v
331 Tests for delayed CRC and defer indication added. igorm 7454d 00h /ethmac/trunk/bench/verilog/tb_ethernet.v
318 Latest Ethernet IP core testbench. tadejm 7785d 21h /ethmac/trunk/bench/verilog/tb_ethernet.v
315 Updated testbench. Some more testcases, some repaired. tadejm 7898d 00h /ethmac/trunk/bench/verilog/tb_ethernet.v
302 mbist signals updated according to newest convention markom 7947d 05h /ethmac/trunk/bench/verilog/tb_ethernet.v
299 Artisan RAMs added. mohor 8005d 01h /ethmac/trunk/bench/verilog/tb_ethernet.v
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 8205d 21h /ethmac/trunk/bench/verilog/tb_ethernet.v
279 Underrun test fixed. Many other tests fixed. mohor 8206d 23h /ethmac/trunk/bench/verilog/tb_ethernet.v
274 Backup version. Not fully working. tadejm 8214d 17h /ethmac/trunk/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 8270d 20h /ethmac/trunk/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 8275d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 8276d 11h /ethmac/trunk/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 8276d 23h /ethmac/trunk/bench/verilog/tb_ethernet.v
254 Temp version. mohor 8278d 16h /ethmac/trunk/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 8278d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 8284d 00h /ethmac/trunk/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 8310d 20h /ethmac/trunk/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 8310d 23h /ethmac/trunk/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 8320d 00h /ethmac/trunk/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 8338d 22h /ethmac/trunk/bench/verilog/tb_ethernet.v
192 Some additional reports added tadej 8340d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
182 Full duplex test improved. tadej 8342d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
181 MIIM test look better. mohor 8342d 22h /ethmac/trunk/bench/verilog/tb_ethernet.v
180 Bench outputs data to display every 128 bytes. mohor 8345d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v

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