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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 348

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Rev Log message Author Age Path
348 Added option to dump VCD files olof 4749d 06h /ethmac/trunk/bench/verilog/tb_ethernet.v
346 Updated project location olof 4749d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
345 Temporarily disable failing tests olof 4749d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
344 bit 9 in phy control register is self clearing olof 4755d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
343 Address miss should not be asserted on short frames olof 4759d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
342 Added cast to avoid inequality when comparing different data types olof 4759d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
338 root 5553d 11h /ethmac/trunk/bench/verilog/tb_ethernet.v
335 New directory structure. root 5610d 16h /ethmac/trunk/bench/verilog/tb_ethernet.v
334 Minor fixes for Icarus simulator. igorm 7058d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
331 Tests for delayed CRC and defer indication added. igorm 7087d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
318 Latest Ethernet IP core testbench. tadejm 7419d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
315 Updated testbench. Some more testcases, some repaired. tadejm 7531d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
302 mbist signals updated according to newest convention markom 7580d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
299 Artisan RAMs added. mohor 7638d 14h /ethmac/trunk/bench/verilog/tb_ethernet.v
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7839d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
279 Underrun test fixed. Many other tests fixed. mohor 7840d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
274 Backup version. Not fully working. tadejm 7848d 06h /ethmac/trunk/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 7904d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 7909d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 7910d 00h /ethmac/trunk/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7910d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
254 Temp version. mohor 7912d 05h /ethmac/trunk/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 7912d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 7917d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 7944d 09h /ethmac/trunk/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 7944d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7953d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 7972d 11h /ethmac/trunk/bench/verilog/tb_ethernet.v
192 Some additional reports added tadej 7974d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
182 Full duplex test improved. tadej 7976d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v

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