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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [trunk/] [rtl/] - Rev 368

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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 2799d 16h /ethmac/trunk/rtl/
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 2862d 13h /ethmac/trunk/rtl/
366 Readded eth_top.v with a deprecation warning olof 2986d 17h /ethmac/trunk/rtl/
365 Whitespace cleanup olof 2987d 16h /ethmac/trunk/rtl/
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 2988d 14h /ethmac/trunk/rtl/
360 Added partial implementation of the debug register from ORPSoC olof 2989d 21h /ethmac/trunk/rtl/
359 Verilator linting fixes olof 2992d 00h /ethmac/trunk/rtl/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 2993d 14h /ethmac/trunk/rtl/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 2993d 14h /ethmac/trunk/rtl/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 2993d 16h /ethmac/trunk/rtl/
355 Import Julius Baxter's verilator hints from ORPSoC olof 2993d 16h /ethmac/trunk/rtl/
354 Whitespace cleanup olof 2993d 17h /ethmac/trunk/rtl/
353 Inherit fixes for bit width of constants from ORPSoC olof 2995d 18h /ethmac/trunk/rtl/
352 Removed delayed assignments from rtl code olof 3000d 00h /ethmac/trunk/rtl/
351 Turn defines into parameters in eth_cop olof 3008d 14h /ethmac/trunk/rtl/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3008d 15h /ethmac/trunk/rtl/
349 Make all parameters configurable from top level olof 3009d 15h /ethmac/trunk/rtl/
346 Updated project location olof 3010d 17h /ethmac/trunk/rtl/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3020d 17h /ethmac/trunk/rtl/
338 root 3814d 19h /ethmac/trunk/rtl/

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