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[/] [ethmac/] [trunk/] [rtl/] - Rev 241

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Rev Log message Author Age Path
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7267d 06h /ethmac/trunk/rtl/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7267d 06h /ethmac/trunk/rtl/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7267d 06h /ethmac/trunk/rtl/
238 Defines fixed to use generic RAM by default. mohor 7279d 11h /ethmac/trunk/rtl/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7281d 16h /ethmac/trunk/rtl/
232 fpga define added. mohor 7287d 10h /ethmac/trunk/rtl/
229 case changed to casex. mohor 7293d 08h /ethmac/trunk/rtl/
227 Changed BIST scan signals. tadejm 7293d 12h /ethmac/trunk/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7293d 13h /ethmac/trunk/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7297d 13h /ethmac/trunk/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7300d 13h /ethmac/trunk/rtl/
218 Typo error fixed. (When using Bist) mohor 7300d 15h /ethmac/trunk/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 7301d 12h /ethmac/trunk/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7301d 12h /ethmac/trunk/rtl/
212 Minor $display change. mohor 7301d 12h /ethmac/trunk/rtl/
211 Bist added. mohor 7301d 12h /ethmac/trunk/rtl/
210 BIST added. mohor 7301d 12h /ethmac/trunk/rtl/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7318d 10h /ethmac/trunk/rtl/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7318d 10h /ethmac/trunk/rtl/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7321d 12h /ethmac/trunk/rtl/

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