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[/] [ethmac/] [trunk/] [rtl/] - Rev 276


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Rev Log message Author Age Path
276 Defer indication changed. tadejm 7364d 08h /ethmac/trunk/rtl
275 Fix MTxErr or prevent sending too big frames. mohor 7371d 12h /ethmac/trunk/rtl
272 When control packets were received, they were ignored in some cases. tadejm 7372d 07h /ethmac/trunk/rtl
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 7373d 09h /ethmac/trunk/rtl
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7374d 09h /ethmac/trunk/rtl
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 7433d 08h /ethmac/trunk/rtl
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
mohor 7433d 19h /ethmac/trunk/rtl
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 7434d 21h /ethmac/trunk/rtl
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 7434d 21h /ethmac/trunk/rtl
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 7434d 21h /ethmac/trunk/rtl
255 TPauseRq synchronized to tx_clk. mohor 7434d 21h /ethmac/trunk/rtl
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7436d 03h /ethmac/trunk/rtl
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 7436d 04h /ethmac/trunk/rtl
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7436d 04h /ethmac/trunk/rtl
248 wb_rst_i is used for MIIM reset. mohor 7437d 04h /ethmac/trunk/rtl
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7440d 07h /ethmac/trunk/rtl
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7441d 03h /ethmac/trunk/rtl
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7441d 23h /ethmac/trunk/rtl
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7441d 23h /ethmac/trunk/rtl
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7441d 23h /ethmac/trunk/rtl

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