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[/] [ethmac/] [trunk/] [rtl/] - Rev 339

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Rev Log message Author Age Path
338 root 5263d 14h /ethmac/trunk/rtl/
335 New directory structure. root 5320d 20h /ethmac/trunk/rtl/
333 Some small fixes + some troubles fixed. igorm 6769d 10h /ethmac/trunk/rtl/
332 Case statement improved for synthesys. igorm 6782d 15h /ethmac/trunk/rtl/
330 Warning fixes. igorm 6797d 17h /ethmac/trunk/rtl/
329 Defer indication fixed. igorm 6797d 18h /ethmac/trunk/rtl/
328 Delayed CRC fixed. igorm 6797d 18h /ethmac/trunk/rtl/
327 Defer indication fixed. igorm 6797d 19h /ethmac/trunk/rtl/
326 Delayed CRC fixed. igorm 6797d 19h /ethmac/trunk/rtl/
325 Defer indication fixed. igorm 6797d 19h /ethmac/trunk/rtl/
323 Accidently deleted line put back. igorm 7094d 19h /ethmac/trunk/rtl/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries		 igorm 7098d 14h /ethmac/trunk/rtl/
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 7098d 18h /ethmac/trunk/rtl/
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7138d 20h /ethmac/trunk/rtl/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7241d 17h /ethmac/trunk/rtl/
306 Lapsus fixed (!we -> ~we). simons 7242d 15h /ethmac/trunk/rtl/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7264d 11h /ethmac/trunk/rtl/
302 mbist signals updated according to newest convention markom 7290d 22h /ethmac/trunk/rtl/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7301d 14h /ethmac/trunk/rtl/
297 Artisan ram instance added. simons 7354d 13h /ethmac/trunk/rtl/

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