URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [trunk/] [rtl/] - Rev 361

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Rev	Log message	Author	Age	Path
360	Added partial implementation of the debug register from ORPSoC	olof	5207d 14h	/ethmac/trunk/rtl/
359	Verilator linting fixes	olof	5209d 17h	/ethmac/trunk/rtl/
358	Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version	olof	5211d 07h	/ethmac/trunk/rtl/
357	Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC	olof	5211d 07h	/ethmac/trunk/rtl/
356	Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure	olof	5211d 09h	/ethmac/trunk/rtl/
355	Import Julius Baxter's verilator hints from ORPSoC	olof	5211d 09h	/ethmac/trunk/rtl/
354	Whitespace cleanup	olof	5211d 10h	/ethmac/trunk/rtl/
353	Inherit fixes for bit width of constants from ORPSoC	olof	5213d 11h	/ethmac/trunk/rtl/
352	Removed delayed assignments from rtl code	olof	5217d 17h	/ethmac/trunk/rtl/
351	Turn defines into parameters in eth_cop	olof	5226d 07h	/ethmac/trunk/rtl/
350	Turn M[1-2]_ADDRESSED_S[1-2] defines into wires	olof	5226d 08h	/ethmac/trunk/rtl/
349	Make all parameters configurable from top level	olof	5227d 08h	/ethmac/trunk/rtl/
346	Updated project location	olof	5228d 10h	/ethmac/trunk/rtl/
341	Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short	olof	5238d 10h	/ethmac/trunk/rtl/
338		root	6032d 12h	/ethmac/trunk/rtl/
335	New directory structure.	root	6089d 18h	/ethmac/trunk/rtl/
333	Some small fixes + some troubles fixed.	igorm	7538d 08h	/ethmac/trunk/rtl/
332	Case statement improved for synthesys.	igorm	7551d 13h	/ethmac/trunk/rtl/
330	Warning fixes.	igorm	7566d 15h	/ethmac/trunk/rtl/
329	Defer indication fixed.	igorm	7566d 16h	/ethmac/trunk/rtl/

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[/] [ethmac/] [trunk/] [rtl/] - Rev 361

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