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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 110

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Rev Log message Author Age Path
110 m_wb_cyc_o signal released after every single transfer. mohor 7297d 12h /ethmac/trunk/rtl/verilog/
109 Comment removed. mohor 7297d 12h /ethmac/trunk/rtl/verilog/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7364d 22h /ethmac/trunk/rtl/verilog/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7373d 23h /ethmac/trunk/rtl/verilog/
104 FCS should not be included in NibbleMinFl. mohor 7375d 17h /ethmac/trunk/rtl/verilog/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 7375d 18h /ethmac/trunk/rtl/verilog/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 7375d 18h /ethmac/trunk/rtl/verilog/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 7375d 18h /ethmac/trunk/rtl/verilog/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 7375d 19h /ethmac/trunk/rtl/verilog/
97 Small typo fixed. lampret 7399d 16h /ethmac/trunk/rtl/verilog/
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 7403d 16h /ethmac/trunk/rtl/verilog/
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 7403d 19h /ethmac/trunk/rtl/verilog/
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 7403d 19h /ethmac/trunk/rtl/verilog/
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 7408d 17h /ethmac/trunk/rtl/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 7409d 19h /ethmac/trunk/rtl/verilog/
91 Comments in Slovene language removed. mohor 7409d 19h /ethmac/trunk/rtl/verilog/
90 casex changed with case, fifo reset changed. mohor 7409d 20h /ethmac/trunk/rtl/verilog/
88 rx_fifo was not always cleared ok. Fixed. mohor 7419d 16h /ethmac/trunk/rtl/verilog/
87 Status was not latched correctly sometimes. Fixed. mohor 7419d 18h /ethmac/trunk/rtl/verilog/
86 Big Endian problem when sending frames fixed. mohor 7421d 01h /ethmac/trunk/rtl/verilog/
85 Log info was missing. mohor 7426d 11h /ethmac/trunk/rtl/verilog/
84 LinkFail signal was not latching appropriate bit. mohor 7426d 11h /ethmac/trunk/rtl/verilog/
83 MAC address recognition was not correct (bytes swaped). mohor 7426d 11h /ethmac/trunk/rtl/verilog/
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 7426d 13h /ethmac/trunk/rtl/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 7430d 15h /ethmac/trunk/rtl/verilog/
79 RetryCntLatched was unused and removed from design mohor 7430d 16h /ethmac/trunk/rtl/verilog/
78 WB_SEL_I was unused and removed from design mohor 7430d 16h /ethmac/trunk/rtl/verilog/
77 Interrupts changed mohor 7430d 16h /ethmac/trunk/rtl/verilog/
76 Interrupts changed in the top file mohor 7430d 16h /ethmac/trunk/rtl/verilog/
75 r_Bro is used for accepting/denying frames mohor 7430d 16h /ethmac/trunk/rtl/verilog/

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