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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 122

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Rev Log message Author Age Path
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 6668d 21h /ethmac/trunk/rtl/verilog/
120 Unused files removed. mohor 6668d 22h /ethmac/trunk/rtl/verilog/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 6668d 22h /ethmac/trunk/rtl/verilog/
118 ShiftEnded synchronization changed. mohor 6672d 13h /ethmac/trunk/rtl/verilog/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 6673d 22h /ethmac/trunk/rtl/verilog/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 6674d 19h /ethmac/trunk/rtl/verilog/
113 RxPointer bug fixed. mohor 6681d 11h /ethmac/trunk/rtl/verilog/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 6682d 01h /ethmac/trunk/rtl/verilog/
111 Master state machine had a bug when switching from master write to
master read.
mohor 6682d 14h /ethmac/trunk/rtl/verilog/
110 m_wb_cyc_o signal released after every single transfer. mohor 6682d 17h /ethmac/trunk/rtl/verilog/
109 Comment removed. mohor 6682d 18h /ethmac/trunk/rtl/verilog/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6750d 04h /ethmac/trunk/rtl/verilog/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 6759d 05h /ethmac/trunk/rtl/verilog/
104 FCS should not be included in NibbleMinFl. mohor 6760d 23h /ethmac/trunk/rtl/verilog/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 6761d 00h /ethmac/trunk/rtl/verilog/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 6761d 00h /ethmac/trunk/rtl/verilog/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 6761d 00h /ethmac/trunk/rtl/verilog/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 6761d 00h /ethmac/trunk/rtl/verilog/
97 Small typo fixed. lampret 6784d 22h /ethmac/trunk/rtl/verilog/
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 6788d 22h /ethmac/trunk/rtl/verilog/

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