OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 133

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 7473d 03h /ethmac/trunk/rtl/verilog/
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7473d 03h /ethmac/trunk/rtl/verilog/
131 LinkFail signal was not latching appropriate bit. mohor 7473d 03h /ethmac/trunk/rtl/verilog/
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 7473d 04h /ethmac/trunk/rtl/verilog/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7493d 03h /ethmac/trunk/rtl/verilog/
126 InvalidSymbol generation changed. mohor 7493d 03h /ethmac/trunk/rtl/verilog/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 7493d 03h /ethmac/trunk/rtl/verilog/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7495d 05h /ethmac/trunk/rtl/verilog/
120 Unused files removed. mohor 7495d 06h /ethmac/trunk/rtl/verilog/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7495d 06h /ethmac/trunk/rtl/verilog/
118 ShiftEnded synchronization changed. mohor 7498d 21h /ethmac/trunk/rtl/verilog/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7500d 06h /ethmac/trunk/rtl/verilog/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7501d 03h /ethmac/trunk/rtl/verilog/
113 RxPointer bug fixed. mohor 7507d 19h /ethmac/trunk/rtl/verilog/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7508d 08h /ethmac/trunk/rtl/verilog/
111 Master state machine had a bug when switching from master write to
master read.
mohor 7508d 22h /ethmac/trunk/rtl/verilog/
110 m_wb_cyc_o signal released after every single transfer. mohor 7509d 01h /ethmac/trunk/rtl/verilog/
109 Comment removed. mohor 7509d 01h /ethmac/trunk/rtl/verilog/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7576d 11h /ethmac/trunk/rtl/verilog/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7585d 13h /ethmac/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.