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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 146

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Rev Log message Author Age Path
118 ShiftEnded synchronization changed. mohor 7944d 16h /ethmac/trunk/rtl/verilog/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7946d 01h /ethmac/trunk/rtl/verilog/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7946d 22h /ethmac/trunk/rtl/verilog/
113 RxPointer bug fixed. mohor 7953d 14h /ethmac/trunk/rtl/verilog/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7954d 04h /ethmac/trunk/rtl/verilog/
111 Master state machine had a bug when switching from master write to
master read.
mohor 7954d 17h /ethmac/trunk/rtl/verilog/
110 m_wb_cyc_o signal released after every single transfer. mohor 7954d 20h /ethmac/trunk/rtl/verilog/
109 Comment removed. mohor 7954d 21h /ethmac/trunk/rtl/verilog/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8022d 07h /ethmac/trunk/rtl/verilog/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8031d 08h /ethmac/trunk/rtl/verilog/

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