OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 147

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7945d 13h /ethmac/trunk/rtl/verilog/
118 ShiftEnded synchronization changed. mohor 7949d 04h /ethmac/trunk/rtl/verilog/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7950d 12h /ethmac/trunk/rtl/verilog/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7951d 09h /ethmac/trunk/rtl/verilog/
113 RxPointer bug fixed. mohor 7958d 01h /ethmac/trunk/rtl/verilog/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7958d 15h /ethmac/trunk/rtl/verilog/
111 Master state machine had a bug when switching from master write to
master read.
mohor 7959d 04h /ethmac/trunk/rtl/verilog/
110 m_wb_cyc_o signal released after every single transfer. mohor 7959d 07h /ethmac/trunk/rtl/verilog/
109 Comment removed. mohor 7959d 08h /ethmac/trunk/rtl/verilog/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8026d 18h /ethmac/trunk/rtl/verilog/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.