OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 165

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
165 HASH improvement needed. mohor 8059d 12h /ethmac/trunk/rtl/verilog/
164 Ethernet debug registers removed. mohor 8059d 12h /ethmac/trunk/rtl/verilog/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 8060d 10h /ethmac/trunk/rtl/verilog/
160 error acknowledge cycle termination added to display. mohor 8060d 10h /ethmac/trunk/rtl/verilog/
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 8061d 06h /ethmac/trunk/rtl/verilog/
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 8065d 04h /ethmac/trunk/rtl/verilog/
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.
mohor 8065d 04h /ethmac/trunk/rtl/verilog/
148 Bug when last byte of destination address was not checked fixed. mohor 8065d 04h /ethmac/trunk/rtl/verilog/
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 8065d 04h /ethmac/trunk/rtl/verilog/
146 CarrierSenseLost status is not set when working in loopback mode. mohor 8065d 04h /ethmac/trunk/rtl/verilog/
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 8065d 04h /ethmac/trunk/rtl/verilog/
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
mohor 8081d 07h /ethmac/trunk/rtl/verilog/
141 Syntax error fixed. mohor 8084d 00h /ethmac/trunk/rtl/verilog/
140 Syntax error fixed. mohor 8084d 00h /ethmac/trunk/rtl/verilog/
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 8084d 00h /ethmac/trunk/rtl/verilog/
138 Synchronous reset added. mohor 8084d 00h /ethmac/trunk/rtl/verilog/
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.
mohor 8084d 01h /ethmac/trunk/rtl/verilog/
136 Parameter ResetValue changed to capital letters. mohor 8084d 10h /ethmac/trunk/rtl/verilog/
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 8086d 03h /ethmac/trunk/rtl/verilog/
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 8086d 04h /ethmac/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.