URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 221

Rev	Log message	Author	Age	Path
149	Signals related to the control frames connected. Debug registers reg1, 2, 3, 4 connected.	mohor	7903d 06h	/ethmac/trunk/rtl/verilog/
148	Bug when last byte of destination address was not checked fixed.	mohor	7903d 06h	/ethmac/trunk/rtl/verilog/
147	ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to the control frames connected.	mohor	7903d 06h	/ethmac/trunk/rtl/verilog/
146	CarrierSenseLost status is not set when working in loopback mode.	mohor	7903d 06h	/ethmac/trunk/rtl/verilog/
145	Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).	mohor	7903d 06h	/ethmac/trunk/rtl/verilog/
143	Only values smaller or equal to 0x80 can be written to TX_BD_NUM register. r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.	mohor	7919d 09h	/ethmac/trunk/rtl/verilog/
141	Syntax error fixed.	mohor	7922d 03h	/ethmac/trunk/rtl/verilog/
140	Syntax error fixed.	mohor	7922d 03h	/ethmac/trunk/rtl/verilog/
139	Synchronous reset added to all registers. Defines used for width. r_MiiMRst changed from bit position 10 to 9.	mohor	7922d 03h	/ethmac/trunk/rtl/verilog/
138	Synchronous reset added.	mohor	7922d 03h	/ethmac/trunk/rtl/verilog/