OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 269

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
229 case changed to casex. mohor 7854d 05h /ethmac/trunk/rtl/verilog/
227 Changed BIST scan signals. tadejm 7854d 08h /ethmac/trunk/rtl/verilog/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7854d 10h /ethmac/trunk/rtl/verilog/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7858d 09h /ethmac/trunk/rtl/verilog/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7861d 10h /ethmac/trunk/rtl/verilog/
218 Typo error fixed. (When using Bist) mohor 7861d 12h /ethmac/trunk/rtl/verilog/
214 Signals for WISHBONE B3 compliant interface added. mohor 7862d 09h /ethmac/trunk/rtl/verilog/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7862d 09h /ethmac/trunk/rtl/verilog/
212 Minor $display change. mohor 7862d 09h /ethmac/trunk/rtl/verilog/
211 Bist added. mohor 7862d 09h /ethmac/trunk/rtl/verilog/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.