OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 280

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7805d 19h /ethmac/trunk/rtl/verilog/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7805d 19h /ethmac/trunk/rtl/verilog/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7805d 19h /ethmac/trunk/rtl/verilog/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7805d 19h /ethmac/trunk/rtl/verilog/
238 Defines fixed to use generic RAM by default. mohor 7817d 23h /ethmac/trunk/rtl/verilog/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7820d 05h /ethmac/trunk/rtl/verilog/
232 fpga define added. mohor 7825d 23h /ethmac/trunk/rtl/verilog/
229 case changed to casex. mohor 7831d 21h /ethmac/trunk/rtl/verilog/
227 Changed BIST scan signals. tadejm 7832d 01h /ethmac/trunk/rtl/verilog/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7832d 02h /ethmac/trunk/rtl/verilog/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.