OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 304

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 6811d 18h /ethmac/trunk/rtl/verilog/
302 mbist signals updated according to newest convention markom 6838d 05h /ethmac/trunk/rtl/verilog/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 6848d 21h /ethmac/trunk/rtl/verilog/
297 Artisan ram instance added. simons 6901d 20h /ethmac/trunk/rtl/verilog/
288 This file was not part of the RTL before, but it should be here. simons 6937d 22h /ethmac/trunk/rtl/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 6964d 01h /ethmac/trunk/rtl/verilog/
285 Binary operator used instead of unary (xnor). mohor 6964d 01h /ethmac/trunk/rtl/verilog/
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 6992d 03h /ethmac/trunk/rtl/verilog/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.
mohor 7019d 20h /ethmac/trunk/rtl/verilog/
280 Reset has priority in some flipflops. mohor 7097d 22h /ethmac/trunk/rtl/verilog/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 7097d 23h /ethmac/trunk/rtl/verilog/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7097d 23h /ethmac/trunk/rtl/verilog/
276 Defer indication changed. tadejm 7097d 23h /ethmac/trunk/rtl/verilog/
275 Fix MTxErr or prevent sending too big frames. mohor 7105d 04h /ethmac/trunk/rtl/verilog/
272 When control packets were received, they were ignored in some cases. tadejm 7105d 23h /ethmac/trunk/rtl/verilog/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 7107d 01h /ethmac/trunk/rtl/verilog/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7108d 01h /ethmac/trunk/rtl/verilog/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 7166d 23h /ethmac/trunk/rtl/verilog/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7167d 11h /ethmac/trunk/rtl/verilog/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 7168d 12h /ethmac/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.