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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 333

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Rev Log message Author Age Path
333 Some small fixes + some troubles fixed. igorm 6352d 12h /ethmac/trunk/rtl/verilog/
332 Case statement improved for synthesys. igorm 6365d 18h /ethmac/trunk/rtl/verilog/
330 Warning fixes. igorm 6380d 20h /ethmac/trunk/rtl/verilog/
329 Defer indication fixed. igorm 6380d 21h /ethmac/trunk/rtl/verilog/
328 Delayed CRC fixed. igorm 6380d 21h /ethmac/trunk/rtl/verilog/
327 Defer indication fixed. igorm 6380d 21h /ethmac/trunk/rtl/verilog/
326 Delayed CRC fixed. igorm 6380d 21h /ethmac/trunk/rtl/verilog/
325 Defer indication fixed. igorm 6380d 22h /ethmac/trunk/rtl/verilog/
323 Accidently deleted line put back. igorm 6677d 22h /ethmac/trunk/rtl/verilog/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 6681d 17h /ethmac/trunk/rtl/verilog/
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 6681d 21h /ethmac/trunk/rtl/verilog/
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 6721d 23h /ethmac/trunk/rtl/verilog/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 6824d 20h /ethmac/trunk/rtl/verilog/
306 Lapsus fixed (!we -> ~we). simons 6825d 18h /ethmac/trunk/rtl/verilog/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 6847d 14h /ethmac/trunk/rtl/verilog/
302 mbist signals updated according to newest convention markom 6874d 01h /ethmac/trunk/rtl/verilog/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 6884d 17h /ethmac/trunk/rtl/verilog/
297 Artisan ram instance added. simons 6937d 16h /ethmac/trunk/rtl/verilog/
288 This file was not part of the RTL before, but it should be here. simons 6973d 18h /ethmac/trunk/rtl/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 6999d 21h /ethmac/trunk/rtl/verilog/

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