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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 351

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Rev Log message Author Age Path
351 Turn defines into parameters in eth_cop olof 4657d 03h /ethmac/trunk/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4657d 04h /ethmac/trunk/rtl/verilog/
349 Make all parameters configurable from top level olof 4658d 04h /ethmac/trunk/rtl/verilog/
346 Updated project location olof 4659d 06h /ethmac/trunk/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4669d 06h /ethmac/trunk/rtl/verilog/
338 root 5463d 08h /ethmac/trunk/rtl/verilog/
335 New directory structure. root 5520d 13h /ethmac/trunk/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 6969d 03h /ethmac/trunk/rtl/verilog/
332 Case statement improved for synthesys. igorm 6982d 09h /ethmac/trunk/rtl/verilog/
330 Warning fixes. igorm 6997d 11h /ethmac/trunk/rtl/verilog/
329 Defer indication fixed. igorm 6997d 12h /ethmac/trunk/rtl/verilog/
328 Delayed CRC fixed. igorm 6997d 12h /ethmac/trunk/rtl/verilog/
327 Defer indication fixed. igorm 6997d 12h /ethmac/trunk/rtl/verilog/
326 Delayed CRC fixed. igorm 6997d 13h /ethmac/trunk/rtl/verilog/
325 Defer indication fixed. igorm 6997d 13h /ethmac/trunk/rtl/verilog/
323 Accidently deleted line put back. igorm 7294d 13h /ethmac/trunk/rtl/verilog/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries		 igorm 7298d 08h /ethmac/trunk/rtl/verilog/
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 7298d 12h /ethmac/trunk/rtl/verilog/
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7338d 14h /ethmac/trunk/rtl/verilog/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7441d 11h /ethmac/trunk/rtl/verilog/
306 Lapsus fixed (!we -> ~we). simons 7442d 09h /ethmac/trunk/rtl/verilog/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7464d 05h /ethmac/trunk/rtl/verilog/
302 mbist signals updated according to newest convention markom 7490d 16h /ethmac/trunk/rtl/verilog/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7501d 08h /ethmac/trunk/rtl/verilog/
297 Artisan ram instance added. simons 7554d 07h /ethmac/trunk/rtl/verilog/
288 This file was not part of the RTL before, but it should be here. simons 7590d 09h /ethmac/trunk/rtl/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7616d 12h /ethmac/trunk/rtl/verilog/
285 Binary operator used instead of unary (xnor). mohor 7616d 12h /ethmac/trunk/rtl/verilog/
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7644d 13h /ethmac/trunk/rtl/verilog/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.		 mohor 7672d 07h /ethmac/trunk/rtl/verilog/

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