OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 354

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 7276d 02h /ethmac/trunk/rtl/verilog/
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7316d 05h /ethmac/trunk/rtl/verilog/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7419d 01h /ethmac/trunk/rtl/verilog/
306 Lapsus fixed (!we -> ~we). simons 7419d 23h /ethmac/trunk/rtl/verilog/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7441d 20h /ethmac/trunk/rtl/verilog/
302 mbist signals updated according to newest convention markom 7468d 06h /ethmac/trunk/rtl/verilog/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7478d 22h /ethmac/trunk/rtl/verilog/
297 Artisan ram instance added. simons 7531d 21h /ethmac/trunk/rtl/verilog/
288 This file was not part of the RTL before, but it should be here. simons 7567d 23h /ethmac/trunk/rtl/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 7594d 02h /ethmac/trunk/rtl/verilog/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.