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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 355

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Rev Log message Author Age Path
355 Import Julius Baxter's verilator hints from ORPSoC olof 4736d 08h /ethmac/trunk/rtl/verilog/
354 Whitespace cleanup olof 4736d 09h /ethmac/trunk/rtl/verilog/
353 Inherit fixes for bit width of constants from ORPSoC olof 4738d 10h /ethmac/trunk/rtl/verilog/
352 Removed delayed assignments from rtl code olof 4742d 16h /ethmac/trunk/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4751d 06h /ethmac/trunk/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4751d 07h /ethmac/trunk/rtl/verilog/
349 Make all parameters configurable from top level olof 4752d 07h /ethmac/trunk/rtl/verilog/
346 Updated project location olof 4753d 09h /ethmac/trunk/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4763d 09h /ethmac/trunk/rtl/verilog/
338 root 5557d 11h /ethmac/trunk/rtl/verilog/
335 New directory structure. root 5614d 17h /ethmac/trunk/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 7063d 07h /ethmac/trunk/rtl/verilog/
332 Case statement improved for synthesys. igorm 7076d 12h /ethmac/trunk/rtl/verilog/
330 Warning fixes. igorm 7091d 14h /ethmac/trunk/rtl/verilog/
329 Defer indication fixed. igorm 7091d 15h /ethmac/trunk/rtl/verilog/
328 Delayed CRC fixed. igorm 7091d 15h /ethmac/trunk/rtl/verilog/
327 Defer indication fixed. igorm 7091d 15h /ethmac/trunk/rtl/verilog/
326 Delayed CRC fixed. igorm 7091d 16h /ethmac/trunk/rtl/verilog/
325 Defer indication fixed. igorm 7091d 16h /ethmac/trunk/rtl/verilog/
323 Accidently deleted line put back. igorm 7388d 16h /ethmac/trunk/rtl/verilog/

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