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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 357

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Rev Log message Author Age Path
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4647d 04h /ethmac/trunk/rtl/verilog/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4647d 06h /ethmac/trunk/rtl/verilog/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4647d 07h /ethmac/trunk/rtl/verilog/
354 Whitespace cleanup olof 4647d 07h /ethmac/trunk/rtl/verilog/
353 Inherit fixes for bit width of constants from ORPSoC olof 4649d 09h /ethmac/trunk/rtl/verilog/
352 Removed delayed assignments from rtl code olof 4653d 15h /ethmac/trunk/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4662d 05h /ethmac/trunk/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4662d 05h /ethmac/trunk/rtl/verilog/
349 Make all parameters configurable from top level olof 4663d 06h /ethmac/trunk/rtl/verilog/
346 Updated project location olof 4664d 08h /ethmac/trunk/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4674d 07h /ethmac/trunk/rtl/verilog/
338 root 5468d 10h /ethmac/trunk/rtl/verilog/
335 New directory structure. root 5525d 15h /ethmac/trunk/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 6974d 05h /ethmac/trunk/rtl/verilog/
332 Case statement improved for synthesys. igorm 6987d 10h /ethmac/trunk/rtl/verilog/
330 Warning fixes. igorm 7002d 12h /ethmac/trunk/rtl/verilog/
329 Defer indication fixed. igorm 7002d 14h /ethmac/trunk/rtl/verilog/
328 Delayed CRC fixed. igorm 7002d 14h /ethmac/trunk/rtl/verilog/
327 Defer indication fixed. igorm 7002d 14h /ethmac/trunk/rtl/verilog/
326 Delayed CRC fixed. igorm 7002d 14h /ethmac/trunk/rtl/verilog/
325 Defer indication fixed. igorm 7002d 15h /ethmac/trunk/rtl/verilog/
323 Accidently deleted line put back. igorm 7299d 15h /ethmac/trunk/rtl/verilog/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries		 igorm 7303d 10h /ethmac/trunk/rtl/verilog/
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 7303d 14h /ethmac/trunk/rtl/verilog/
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7343d 16h /ethmac/trunk/rtl/verilog/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7446d 13h /ethmac/trunk/rtl/verilog/
306 Lapsus fixed (!we -> ~we). simons 7447d 10h /ethmac/trunk/rtl/verilog/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7469d 07h /ethmac/trunk/rtl/verilog/
302 mbist signals updated according to newest convention markom 7495d 17h /ethmac/trunk/rtl/verilog/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7506d 10h /ethmac/trunk/rtl/verilog/

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