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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 359

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Rev Log message Author Age Path
359 Verilator linting fixes olof 4020d 05h /ethmac/trunk/rtl/verilog/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4021d 19h /ethmac/trunk/rtl/verilog/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4021d 19h /ethmac/trunk/rtl/verilog/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4021d 21h /ethmac/trunk/rtl/verilog/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4021d 22h /ethmac/trunk/rtl/verilog/
354 Whitespace cleanup olof 4021d 22h /ethmac/trunk/rtl/verilog/
353 Inherit fixes for bit width of constants from ORPSoC olof 4024d 00h /ethmac/trunk/rtl/verilog/
352 Removed delayed assignments from rtl code olof 4028d 06h /ethmac/trunk/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4036d 20h /ethmac/trunk/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4036d 20h /ethmac/trunk/rtl/verilog/
349 Make all parameters configurable from top level olof 4037d 21h /ethmac/trunk/rtl/verilog/
346 Updated project location olof 4038d 23h /ethmac/trunk/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4048d 23h /ethmac/trunk/rtl/verilog/
338 root 4843d 01h /ethmac/trunk/rtl/verilog/
335 New directory structure. root 4900d 06h /ethmac/trunk/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 6348d 20h /ethmac/trunk/rtl/verilog/
332 Case statement improved for synthesys. igorm 6362d 02h /ethmac/trunk/rtl/verilog/
330 Warning fixes. igorm 6377d 03h /ethmac/trunk/rtl/verilog/
329 Defer indication fixed. igorm 6377d 05h /ethmac/trunk/rtl/verilog/
328 Delayed CRC fixed. igorm 6377d 05h /ethmac/trunk/rtl/verilog/

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