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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 367

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Rev Log message Author Age Path
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 4511d 06h /ethmac/trunk/rtl/verilog/
366 Readded eth_top.v with a deprecation warning olof 4635d 10h /ethmac/trunk/rtl/verilog/
365 Whitespace cleanup olof 4636d 09h /ethmac/trunk/rtl/verilog/
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4637d 07h /ethmac/trunk/rtl/verilog/
360 Added partial implementation of the debug register from ORPSoC olof 4638d 14h /ethmac/trunk/rtl/verilog/
359 Verilator linting fixes olof 4640d 16h /ethmac/trunk/rtl/verilog/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4642d 06h /ethmac/trunk/rtl/verilog/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4642d 07h /ethmac/trunk/rtl/verilog/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4642d 08h /ethmac/trunk/rtl/verilog/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4642d 09h /ethmac/trunk/rtl/verilog/
354 Whitespace cleanup olof 4642d 10h /ethmac/trunk/rtl/verilog/
353 Inherit fixes for bit width of constants from ORPSoC olof 4644d 11h /ethmac/trunk/rtl/verilog/
352 Removed delayed assignments from rtl code olof 4648d 17h /ethmac/trunk/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4657d 07h /ethmac/trunk/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4657d 07h /ethmac/trunk/rtl/verilog/
349 Make all parameters configurable from top level olof 4658d 08h /ethmac/trunk/rtl/verilog/
346 Updated project location olof 4659d 10h /ethmac/trunk/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4669d 10h /ethmac/trunk/rtl/verilog/
338 root 5463d 12h /ethmac/trunk/rtl/verilog/
335 New directory structure. root 5520d 17h /ethmac/trunk/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 6969d 07h /ethmac/trunk/rtl/verilog/
332 Case statement improved for synthesys. igorm 6982d 13h /ethmac/trunk/rtl/verilog/
330 Warning fixes. igorm 6997d 15h /ethmac/trunk/rtl/verilog/
329 Defer indication fixed. igorm 6997d 16h /ethmac/trunk/rtl/verilog/
328 Delayed CRC fixed. igorm 6997d 16h /ethmac/trunk/rtl/verilog/
327 Defer indication fixed. igorm 6997d 16h /ethmac/trunk/rtl/verilog/
326 Delayed CRC fixed. igorm 6997d 16h /ethmac/trunk/rtl/verilog/
325 Defer indication fixed. igorm 6997d 17h /ethmac/trunk/rtl/verilog/
323 Accidently deleted line put back. igorm 7294d 17h /ethmac/trunk/rtl/verilog/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries		 igorm 7298d 12h /ethmac/trunk/rtl/verilog/

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