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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 368

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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 3831d 04h /ethmac/trunk/rtl/verilog/
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 3894d 01h /ethmac/trunk/rtl/verilog/
366 Readded eth_top.v with a deprecation warning olof 4018d 05h /ethmac/trunk/rtl/verilog/
365 Whitespace cleanup olof 4019d 04h /ethmac/trunk/rtl/verilog/
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4020d 02h /ethmac/trunk/rtl/verilog/
360 Added partial implementation of the debug register from ORPSoC olof 4021d 09h /ethmac/trunk/rtl/verilog/
359 Verilator linting fixes olof 4023d 12h /ethmac/trunk/rtl/verilog/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4025d 02h /ethmac/trunk/rtl/verilog/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4025d 02h /ethmac/trunk/rtl/verilog/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4025d 04h /ethmac/trunk/rtl/verilog/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4025d 04h /ethmac/trunk/rtl/verilog/
354 Whitespace cleanup olof 4025d 05h /ethmac/trunk/rtl/verilog/
353 Inherit fixes for bit width of constants from ORPSoC olof 4027d 06h /ethmac/trunk/rtl/verilog/
352 Removed delayed assignments from rtl code olof 4031d 12h /ethmac/trunk/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4040d 02h /ethmac/trunk/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4040d 03h /ethmac/trunk/rtl/verilog/
349 Make all parameters configurable from top level olof 4041d 03h /ethmac/trunk/rtl/verilog/
346 Updated project location olof 4042d 05h /ethmac/trunk/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4052d 05h /ethmac/trunk/rtl/verilog/
338 root 4846d 07h /ethmac/trunk/rtl/verilog/
335 New directory structure. root 4903d 13h /ethmac/trunk/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 6352d 03h /ethmac/trunk/rtl/verilog/
332 Case statement improved for synthesys. igorm 6365d 08h /ethmac/trunk/rtl/verilog/
330 Warning fixes. igorm 6380d 10h /ethmac/trunk/rtl/verilog/
329 Defer indication fixed. igorm 6380d 11h /ethmac/trunk/rtl/verilog/
328 Delayed CRC fixed. igorm 6380d 11h /ethmac/trunk/rtl/verilog/
327 Defer indication fixed. igorm 6380d 11h /ethmac/trunk/rtl/verilog/
326 Delayed CRC fixed. igorm 6380d 12h /ethmac/trunk/rtl/verilog/
325 Defer indication fixed. igorm 6380d 12h /ethmac/trunk/rtl/verilog/
323 Accidently deleted line put back. igorm 6677d 12h /ethmac/trunk/rtl/verilog/

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