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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 368

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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 3876d 03h /ethmac/trunk/rtl/verilog
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 3939d 00h /ethmac/trunk/rtl/verilog
366 Readded eth_top.v with a deprecation warning olof 4063d 04h /ethmac/trunk/rtl/verilog
365 Whitespace cleanup olof 4064d 03h /ethmac/trunk/rtl/verilog
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4065d 01h /ethmac/trunk/rtl/verilog
360 Added partial implementation of the debug register from ORPSoC olof 4066d 08h /ethmac/trunk/rtl/verilog
359 Verilator linting fixes olof 4068d 10h /ethmac/trunk/rtl/verilog
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4070d 00h /ethmac/trunk/rtl/verilog
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4070d 01h /ethmac/trunk/rtl/verilog
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4070d 02h /ethmac/trunk/rtl/verilog
355 Import Julius Baxter's verilator hints from ORPSoC olof 4070d 03h /ethmac/trunk/rtl/verilog
354 Whitespace cleanup olof 4070d 04h /ethmac/trunk/rtl/verilog
353 Inherit fixes for bit width of constants from ORPSoC olof 4072d 05h /ethmac/trunk/rtl/verilog
352 Removed delayed assignments from rtl code olof 4076d 11h /ethmac/trunk/rtl/verilog
351 Turn defines into parameters in eth_cop olof 4085d 01h /ethmac/trunk/rtl/verilog
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4085d 01h /ethmac/trunk/rtl/verilog
349 Make all parameters configurable from top level olof 4086d 02h /ethmac/trunk/rtl/verilog
346 Updated project location olof 4087d 04h /ethmac/trunk/rtl/verilog
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4097d 04h /ethmac/trunk/rtl/verilog
338 root 4891d 06h /ethmac/trunk/rtl/verilog

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