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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 78

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Rev Log message Author Age Path
78 WB_SEL_I was unused and removed from design mohor 7479d 04h /ethmac/trunk/rtl/verilog/
77 Interrupts changed mohor 7479d 04h /ethmac/trunk/rtl/verilog/
76 Interrupts changed in the top file mohor 7479d 04h /ethmac/trunk/rtl/verilog/
75 r_Bro is used for accepting/denying frames mohor 7479d 04h /ethmac/trunk/rtl/verilog/
74 Reset values are passed to registers through parameters mohor 7479d 04h /ethmac/trunk/rtl/verilog/
73 Number of interrupts changed mohor 7479d 04h /ethmac/trunk/rtl/verilog/
72 Retry is not activated when a Tx Underrun occured mohor 7483d 07h /ethmac/trunk/rtl/verilog/
70 Small fixes. mohor 7487d 10h /ethmac/trunk/rtl/verilog/
69 Define missmatch fixed. mohor 7488d 07h /ethmac/trunk/rtl/verilog/
68 Registered trimmed. Unused registers removed. mohor 7489d 06h /ethmac/trunk/rtl/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 7489d 07h /ethmac/trunk/rtl/verilog/
65 Testbench fixed, code simplified, unused signals removed. mohor 7489d 13h /ethmac/trunk/rtl/verilog/
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 7490d 03h /ethmac/trunk/rtl/verilog/
63 RxAbort is connected differently. mohor 7490d 07h /ethmac/trunk/rtl/verilog/
62 RxAbort is an output. No need to have is declared as wire. mohor 7490d 07h /ethmac/trunk/rtl/verilog/
61 RxStartFrm cleared when abort or retry comes. mohor 7490d 08h /ethmac/trunk/rtl/verilog/
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 7490d 08h /ethmac/trunk/rtl/verilog/
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 7490d 09h /ethmac/trunk/rtl/verilog/
58 File format changed. mohor 7490d 09h /ethmac/trunk/rtl/verilog/
57 Format of the file changed a bit. mohor 7490d 09h /ethmac/trunk/rtl/verilog/

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