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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 86

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Rev Log message Author Age Path
86 Big Endian problem when sending frames fixed. mohor 8173d 00h /ethmac/trunk/rtl/verilog/
85 Log info was missing. mohor 8178d 10h /ethmac/trunk/rtl/verilog/
84 LinkFail signal was not latching appropriate bit. mohor 8178d 10h /ethmac/trunk/rtl/verilog/
83 MAC address recognition was not correct (bytes swaped). mohor 8178d 10h /ethmac/trunk/rtl/verilog/
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8178d 12h /ethmac/trunk/rtl/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 8182d 14h /ethmac/trunk/rtl/verilog/
79 RetryCntLatched was unused and removed from design mohor 8182d 15h /ethmac/trunk/rtl/verilog/
78 WB_SEL_I was unused and removed from design mohor 8182d 15h /ethmac/trunk/rtl/verilog/
77 Interrupts changed mohor 8182d 15h /ethmac/trunk/rtl/verilog/
76 Interrupts changed in the top file mohor 8182d 15h /ethmac/trunk/rtl/verilog/
75 r_Bro is used for accepting/denying frames mohor 8182d 15h /ethmac/trunk/rtl/verilog/
74 Reset values are passed to registers through parameters mohor 8182d 15h /ethmac/trunk/rtl/verilog/
73 Number of interrupts changed mohor 8182d 15h /ethmac/trunk/rtl/verilog/
72 Retry is not activated when a Tx Underrun occured mohor 8186d 18h /ethmac/trunk/rtl/verilog/
70 Small fixes. mohor 8190d 20h /ethmac/trunk/rtl/verilog/
69 Define missmatch fixed. mohor 8191d 18h /ethmac/trunk/rtl/verilog/
68 Registered trimmed. Unused registers removed. mohor 8192d 17h /ethmac/trunk/rtl/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8192d 18h /ethmac/trunk/rtl/verilog/
65 Testbench fixed, code simplified, unused signals removed. mohor 8193d 00h /ethmac/trunk/rtl/verilog/
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 8193d 14h /ethmac/trunk/rtl/verilog/

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