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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_cop.v] - Rev 352

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Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 3459d 04h /ethmac/trunk/rtl/verilog/eth_cop.v
351 Turn defines into parameters in eth_cop olof 3467d 18h /ethmac/trunk/rtl/verilog/eth_cop.v
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3467d 18h /ethmac/trunk/rtl/verilog/eth_cop.v
346 Updated project location olof 3469d 21h /ethmac/trunk/rtl/verilog/eth_cop.v
338 root 4273d 23h /ethmac/trunk/rtl/verilog/eth_cop.v
335 New directory structure. root 4331d 04h /ethmac/trunk/rtl/verilog/eth_cop.v
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 6427d 02h /ethmac/trunk/rtl/verilog/eth_cop.v
212 Minor $display change. mohor 6672d 22h /ethmac/trunk/rtl/verilog/eth_cop.v
160 error acknowledge cycle termination added to display. mohor 6704d 01h /ethmac/trunk/rtl/verilog/eth_cop.v
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 6729d 21h /ethmac/trunk/rtl/verilog/eth_cop.v

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