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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_fifo.v] - Rev 357

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357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3776d 02h /ethmac/trunk/rtl/verilog/eth_fifo.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3776d 03h /ethmac/trunk/rtl/verilog/eth_fifo.v
354 Whitespace cleanup olof 3776d 04h /ethmac/trunk/rtl/verilog/eth_fifo.v
352 Removed delayed assignments from rtl code olof 3782d 12h /ethmac/trunk/rtl/verilog/eth_fifo.v
346 Updated project location olof 3793d 05h /ethmac/trunk/rtl/verilog/eth_fifo.v
338 root 4597d 07h /ethmac/trunk/rtl/verilog/eth_fifo.v
335 New directory structure. root 4654d 12h /ethmac/trunk/rtl/verilog/eth_fifo.v
330 Warning fixes. igorm 6131d 10h /ethmac/trunk/rtl/verilog/eth_fifo.v
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 7167d 09h /ethmac/trunk/rtl/verilog/eth_fifo.v
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 7195d 09h /ethmac/trunk/rtl/verilog/eth_fifo.v
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.
mohor 7243d 06h /ethmac/trunk/rtl/verilog/eth_fifo.v

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