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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_macstatus.v] - Rev 352

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Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 3466d 17h /ethmac/trunk/rtl/verilog/eth_macstatus.v
346 Updated project location olof 3477d 10h /ethmac/trunk/rtl/verilog/eth_macstatus.v
338 root 4281d 12h /ethmac/trunk/rtl/verilog/eth_macstatus.v
335 New directory structure. root 4338d 17h /ethmac/trunk/rtl/verilog/eth_macstatus.v
333 Some small fixes + some troubles fixed. igorm 5787d 07h /ethmac/trunk/rtl/verilog/eth_macstatus.v
325 Defer indication fixed. igorm 5815d 17h /ethmac/trunk/rtl/verilog/eth_macstatus.v
276 Defer indication changed. tadejm 6568d 14h /ethmac/trunk/rtl/verilog/eth_macstatus.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 6638d 01h /ethmac/trunk/rtl/verilog/eth_macstatus.v
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6646d 05h /ethmac/trunk/rtl/verilog/eth_macstatus.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 6708d 12h /ethmac/trunk/rtl/verilog/eth_macstatus.v
146 CarrierSenseLost status is not set when working in loopback mode. mohor 6716d 09h /ethmac/trunk/rtl/verilog/eth_macstatus.v
126 InvalidSymbol generation changed. mohor 6757d 09h /ethmac/trunk/rtl/verilog/eth_macstatus.v
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 6851d 13h /ethmac/trunk/rtl/verilog/eth_macstatus.v
70 Small fixes. mohor 6914d 17h /ethmac/trunk/rtl/verilog/eth_macstatus.v
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 6917d 10h /ethmac/trunk/rtl/verilog/eth_macstatus.v
43 Tx status is written back to the BD. mohor 6921d 18h /ethmac/trunk/rtl/verilog/eth_macstatus.v
42 Rx status is written back to the BD. mohor 6924d 11h /ethmac/trunk/rtl/verilog/eth_macstatus.v
37 Link in the header changed. mohor 6940d 17h /ethmac/trunk/rtl/verilog/eth_macstatus.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7036d 18h /ethmac/trunk/rtl/verilog/eth_macstatus.v
18 Few little NCSIM warnings fixed. mohor 7074d 13h /ethmac/trunk/rtl/verilog/eth_macstatus.v

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