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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_miim.v] - Rev 354


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Rev Log message Author Age Path
354 Whitespace cleanup olof 4727d 09h /ethmac/trunk/rtl/verilog/eth_miim.v
352 Removed delayed assignments from rtl code olof 4733d 17h /ethmac/trunk/rtl/verilog/eth_miim.v
349 Make all parameters configurable from top level olof 4743d 08h /ethmac/trunk/rtl/verilog/eth_miim.v
346 Updated project location olof 4744d 09h /ethmac/trunk/rtl/verilog/eth_miim.v
338 root 5548d 12h /ethmac/trunk/rtl/verilog/eth_miim.v
335 New directory structure. root 5605d 17h /ethmac/trunk/rtl/verilog/eth_miim.v
333 Some small fixes + some troubles fixed. igorm 7054d 07h /ethmac/trunk/rtl/verilog/eth_miim.v
330 Warning fixes. igorm 7082d 14h /ethmac/trunk/rtl/verilog/eth_miim.v
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7729d 17h /ethmac/trunk/rtl/verilog/eth_miim.v
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 8004d 09h /ethmac/trunk/rtl/verilog/eth_miim.v
37 Link in the header changed. mohor 8207d 17h /ethmac/trunk/rtl/verilog/eth_miim.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8303d 18h /ethmac/trunk/rtl/verilog/eth_miim.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 8377d 12h /ethmac/trunk/rtl/verilog/eth_miim.v

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