OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_outputcontrol.v] - Rev 352

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 3461d 03h /ethmac/trunk/rtl/verilog/eth_outputcontrol.v
346 Updated project location olof 3471d 20h /ethmac/trunk/rtl/verilog/eth_outputcontrol.v
338 root 4275d 22h /ethmac/trunk/rtl/verilog/eth_outputcontrol.v
335 New directory structure. root 4333d 03h /ethmac/trunk/rtl/verilog/eth_outputcontrol.v
109 Comment removed. mohor 6767d 17h /ethmac/trunk/rtl/verilog/eth_outputcontrol.v
37 Link in the header changed. mohor 6935d 03h /ethmac/trunk/rtl/verilog/eth_outputcontrol.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7031d 05h /ethmac/trunk/rtl/verilog/eth_outputcontrol.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7104d 23h /ethmac/trunk/rtl/verilog/eth_outputcontrol.v

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.